1. Field of the Invention
The present invention generally relates to high bandwidth, narrow input/output (I/O) Dynamic Random Access Memories (DRAMs) and, more particularly, to a DRAM capable of stacking commands and self initiating execution of pending operations to provide continuous input/output data streams.
2. Description of the Related Art
Dynamic random access memory (DRAM) performance is a well known limitation to computer system performance. Processor speeds are rapidly outpacing main memory performance, with both processor designers and system manufacturers developing higher performance memory subsystems in an effort to minimize performance limitations due to the slower DRAM devices. Ideally, the memory performance would match or exceed processor performance, i.e., a memory cycle time would be less than one processor clock cycle. This is almost never the case and, so, the memory is a system bottleneck. For example, a state of the art high speed microprocessor may be based on a 333 MegaHertz (MHZ) clock with a 3 nanosecond (ns) clock period. A high performance synchronous DRAM (SDRAM) may have a 36 ns access time, which falls far short of processor performance.
This system bottleneck is exacerbated by the rise in popularity of multimedia applications. Multimedia applications demand several times more bandwidth for main memory or frame-buffer memory than computational intensive tasks such as spread sheet analysis programs or, other input/output (I/O) intensive applications such as word processing or printing.
Extended Data Out (EDO) and Synchronous DRAMs (SDRAMs) were developed to improve bandwidth. However, SDRAMs and EDO RAMs still do not match processor performance and, therefore, still limit system performance. Consequently, as faster microprocessors are developed for multimedia processing and high performance systems, faster memory architecture is being developed to bridge the memory/processor performance gap, e.g., wide I/O SDRAMs and double data rate (DDR) SDRAMs.
Recent developments predict a major turning point for memory devices and related subsystems with a shift to high speed/narrow I/O devices. These high bandwidth (data rate)DRAMs achieve the high data rate by accessing a large number of bits in an array, then multiplexing by 8:1 to achieve clocked data rates in excess of 500 MHZ.
High bandwidth architectures have been proposed for Dynamic Random Access Memories (DRAMs) that reduce chip pin count to nine pins by multiplexing input commands, addresses and data. For example, see U.S. Pat. No. 5,430,676 to Ware et al., entitled "Dynamic Random Access Memory System," U.S. Pat. No. 5,434,817 to Ware et al., entitled "Dynamic Random Access Memory System," and U.S. Pat. No. 5,511,024 to Ware et al., entitled "Dynamic Random Access Memory System."
In these high bandwidth DRAM architectures, commands are serially input on the nine pins at a 533 MHZ clock rate. Packets of control information called "Request Packets" are transferred to and stored in the DRAM during what is termed a transaction operation. After a pre-specified latency period, data is either input or output at a 533 MHZ transfer rate.
Request packets include a device, bank, and row address of a page to be activated, the column address of the first of eight bytes (an octo-byte) to be read, and a Data packet. A Data packet includes input data and data masking command.
Bus switching rates during these command or data transactions place stringent requirements on system bus net. Since all system communication and handshaking with the DRAM is through the nine bit bus, parallel system operations become difficult. Although the high bandwidth architecture may provide a faster data transfer rate than other high bandwidth RAM alternatives, bus contentions and bus blocking may result to reduce overall system performance and prevent seamless data transfers.
To maintain a seamless data I/O it would be necessary to issue commands early, which is not permitted in current devices. However, doing so would likely result in an unknown condition on the data bus or in issuing data out of order.